I²C Communication Simulator

Editable defaults · live clock/data waveform · correct master/slave direction

Slave 1 settings (defaults loaded)
Slave 2 settings (defaults loaded)
SDA SCL Master Controls bus Addr: 0x— Slave 1 Addr: 0x48 Idle reg 0x1C · data 0xA5 Slave 2 Addr: 0x76 Idle reg 0x04 · data 0x3F R↑ 4.7kΩ R↑ 4.7kΩ VCC (3.3V / 5V) CLK DATA Live waveform appears here during each byte transfer
Defaults are loaded. Edit any address/data field if needed, then start a transaction…
SDA — data line SCL — clock line Master → Slave byte Slave → Master byte ACK / NACK sender shown correctly
DATA now stays on its own baseline like CLK: bit 1 is drawn above the baseline, bit 0 stays on the baseline. Waveforms are drawn live while the communication animation runs.