SPI Communication Simulator

Full-duplex bus · timing diagram · bit time labels · adjustable clock speed

Bus: Idle CLK low · sample rising
T = 2.00 µs
Slave 1 — MOSI / MISO bytes
Slave 2 — MOSI / MISO bytes
MOSI MISO SCLK CS0 CS1 Master Controls CLK Mode 0 Full duplex Slave 1 Idle MOSI 0xA5 · MISO 0x3C Slave 2 Idle MOSI 0x76 · MISO 0xB2 CS active-low · driven by master
Timing diagram appears after transfer SCLK MOSI MISO CS 1 0 1 0 1 0 1 0
Bit decode appears after transfer…
Configure bytes above, pick SPI mode, then start a transfer…
MOSI MISO SCLK CS0 CS1 Sample ▲
SPI timing: CS goes LOW → CLK idles at CPOL level → data shifts on one clock edge, sampled on the opposite. Tbit = 1 / f_clk. Each bit cell shows its time duration. Dashed markers show sample points per CPHA.